1. Field of the Invention
The present invention relates generally to a method of fabricating an epitaxial layer, and more specifically, to a method of fabricating an epitaxial layer performed in a hydrogen-free atmosphere and at a temperature lower than 800° C. thereby making the interface between the epitaxial layer and the substrate have a square shape.
2. Description of the Prior Art
As known in the art, strained silicon technologies have been introduced in the MOS manufacturing process in order to increase the mobility of electrons or holes, thereby attaining higher performance of a semiconductor device. For example, taking advantage of the lattice constant of a SiGe layer being different from that of Si, a strain occurs in the silicon layer growing on the SiGe layer. Since SiGe has a larger lattice constant than Si, the band structure of Si is altered, thereby increasing the mobility of the carriers.
FIG. 1 schematically depicts a cross-sectional view of a conventional MOS transistor using epitaxial technologies. As shown in FIG. 1, the steps of fabricating the MOS transistor 100 include forming a gate structure 120 on the substrate 110, wherein the gate structure 120 includes a gate dielectric layer 122, a gate electrode 124 and a cap layer 126. A spacer 130 is formed on the sides of the gate structure 120, wherein the spacer 130 is a single layer structure or multi-layer structure composed of silicon nitride or silicon oxide, but is not limited thereto. Automatically aligning and etching a recess 140 is performed by using the spacer 130 and the gate structure 120 as hard masks. A 800° C. pre-baking process accompanied with hydrogen imported is preformed to clean the surface of the recess 140. A process such as a Si seed layer deposition process, a Si epitaxial growth process, a Si cap layer process, etc. is performed to form an epitaxial layer 150 in the recess 140. Otherwise, a trench isolation structure 10 is formed surrounding the MOS transistor 100 to electrically isolate each MOS transistors.
In modern processes, a precursor of chlorine containing gases such as hexachlorodisilane (HCD) is imported as the spacer 130 is formed, thereby allowing chlorine to attach on the surface of the spacer 130 and the recess 140. And then, the interface between the epitaxial layer 150 and the substrate 110 is passivated into an arc shape as the 800° C. pre-baking process accompanied with hydrogen imported is performed. As a result, rounding makes the width of SiGe to gate reduction leading to higher stress on channel by SiGe layer 150. However, it's hard to control the level of rounding shape which causes the instability of electrical performance of MOS transistor 100.